Power electronics and battery systems
Rails that hold under load, batteries that report honestly, and shutdowns that don't corrupt storage.
Power is the subsystem that decides whether a product is reliable. Signal integrity problems announce themselves; power problems show up as a field failure rate nobody can reproduce on a desk.
Rails that hold under real load
An edge-AI SoC running inference is not the same load as the same SoC idling. Rails get designed against the worst realistic transient at the worst realistic ambient — not the typical figures on page one of the datasheet. Sequencing follows each device’s specification exactly, because a processor brought up out of order can latch or simply refuse to boot.
Where the money and the risk are
| Decision | What it actually governs |
|---|---|
| Topology and magnetics | BOM cost at volume, efficiency, and how much board area the power section eats |
| Transient headroom | Whether a rail holds when an edge-AI SoC starts inferring, not when it idles |
| Sequencing | Whether the processor comes out of reset at all — out of order it can latch or simply refuse |
| Voltage derating | Survival of connection transients, which are routinely near twice the nominal rail |
| Mechanical derating | Ceramic capacitors crack under board flex; the failure looks electrical and is not |
| Measurement path | Whether the current you read is the current that is flowing |
Component selection follows from those decisions rather than driving them. We have used a few hundred regulators over the years; which ones is far less interesting than why.
Losing power gracefully
Any product that writes to flash needs a plan for power loss. Battery-disconnect detection, enough hold-up energy for the longest realistic write, and an early signal to firmware — sized properly, so the shutdown completes rather than nearly completes.
Always-on and low-power
Where the product runs from a battery, the quiescent path matters more than the peak. LDO selection, sleep-state current, wake sources and the sensors that stay alive get budgeted at architecture stage, because a design that missed its sleep budget cannot be fixed at layout.
Common questions
Straight answers
What is dying-gasp and why does it matter?
It is the moment between losing input power and the rails collapsing. If nothing handles it, the filesystem is mid-write and the product boots corrupted. The fix is hold-up energy plus an early warning signal so firmware can flush and unmount — designed in, sized against real worst-case write time. We have implemented battery-disconnect and dying-gasp shutdown paths using integrated hold-up controllers such as the MPS MP5515.
Do you design full battery management systems?
We design the front-end: high-side switching, MOSFET selection against real fault currents, isolated current sensing, protection, and the interface to a fuel-gauge or BMS controller. A full multi-cell safety-certified BMS carrying its own compliance evidence is a specialist product — for that we integrate rather than reinvent.
Why does hot-plug need special attention?
Plugging a live connector into a board with bulk capacitance produces an inrush current and an LC ring that can exceed the input rating of parts downstream. On a board people will plug and unplug in the field, that is a reliability problem — solved with inrush limiting, reverse-blocking control such as the LM74700-Q1, and correct capacitor selection.
Can you help hit a unit cost target?
Yes, and power is usually where the money is. Topology, magnetics and capacitor choices swing BOM cost significantly. We have taken designs to defined unit-cost targets at volume, with second sources on the parts most likely to go short.
Evidence
Where this has been applied
Edge-compute architecture for an unmanned surface vessel
Three architectures compared on real bandwidth budgets, so the platform decision was made on evidence rather than TOPS figures.
Flight-controller carrier for a tube-launched UAV
Teardown, clean-room re-implementation, and a rigid-flex carrier that fits inside a launch tube.