50 Ω trace width calculator
Trace width for a target impedance, from your actual stack-up. Change any input and the result updates.
Trace width
—mm
— mil
A starting number, not a manufacturing instruction. Send the stack-up to your fabricator and let their field solver set the final width.
The formulas
These are the IPC-2141 closed-form approximations. They are shown so you can check the result rather than trust it.
Microstrip
Z₀ = 87 / √(εr + 1.41) · ln( 5.98·h / (0.8·w + t) )Stripline
Z₀ = 60 / √(εr) · ln( 1.9·b / (0.8·w + t) )where b is the plate-to-plate separation, taken as 2·h.
Differential
Z_diff ≈ 2·Z₀ · (1 − 0.48·e^(−0.96·s/h)) (microstrip)
Z_diff ≈ 2·Z₀ · (1 − 0.347·e^(−2.9·s/h)) (stripline)
The calculator solves these numerically for w, so the differential
result accounts for the coupling between the traces rather than just doubling a
single-ended width.
Where this stops being accurate
- Solder mask lowers microstrip impedance by roughly 1–2 Ω. Not modelled here.
- Copper roughness matters above a few GHz and is not modelled.
- Glass-weave skew affects tight differential pairs on coarse weaves.
- Frequency-dependent εr — FR-4 permittivity falls with frequency.
- Etch factor — the finished trace is trapezoidal, not rectangular.
For controlled-impedance production the fabricator runs a 2D field solver on the real stack-up and adjusts the width to hit your target, usually to ±10%. That conversation is the one that matters; this calculator just gets you to it with a sensible starting point.
Related: PCB design services · RF and connectivity · bend radius calculator
Stack-up not settled yet?
Impedance you assumed is not impedance you have. Send us the layer count, the interfaces and your fabricator, and we'll tell you what the stack-up needs to be.