Decoupling network designer
Target impedance, plotted against frequency, with the anti-resonance peaks that make a rail worse when you add the wrong capacitor.
Target impedance
—mΩ
—
The physics
Target impedance
Z_target = (Vdd × ripple) / ΔI
A load step of ΔI through a network of impedance Z
produces a rail excursion of ΔI · Z. Fix the excursion you can
tolerate and the target follows. It is the same reasoning as sizing a resistor
for a voltage drop, applied across frequency instead of at DC.
A capacitor is not a capacitor
Z(f) = √( ESR² + ( 2πf·L_total − 1/(2πf·C) )² )
L_total = ESL_part + L_mounting
Below self-resonance the 1/2πfC term dominates and impedance falls
with frequency. Above it, 2πfL dominates and impedance rises. At
resonance the reactive terms cancel and only ESR is left, which is the minimum
that capacitor can ever present.
f_SRF = 1 / (2π · √(L_total · C))Mounting inductance moves that frequency down. A 100 nF part with 0.6 nH of its own ESL and 1.5 nH of mounting loop resonates at roughly half the frequency the datasheet implies — and the layout, not the part, decided that.
Banks in parallel, and the trap
1/Z_total = Σ 1/Z_i (complex, not magnitudes)Here is the part that catches people. Between two banks there is a frequency where the larger capacitor is already inductive and the smaller one is still capacitive. An inductor in parallel with a capacitor is a tank circuit, and at its resonance the parallel combination presents a high impedance — a peak that can exceed what either bank shows alone.
This is why fitting one of every value is not automatically better. Each extra distinct value introduces another peak. Two values with several parts in each bank is very often flatter than three values with one part each — and the plot above will show you that directly if you drag the counts.
What actually moves the curve
- Mounting inductance, first and always. Shorter vias, thinner dielectric to the plane, wide pad entry. Above tens of megahertz this is the whole game.
- More parts per bank divides both ESR and inductance, lowering impedance and flattening peaks. Usually better value than another distinct capacitance.
- ESR is not the enemy. A little damps anti-resonance. All-ceramic networks with very low ESR produce sharper peaks than networks with some tantalum or polymer bulk.
- The plane pair itself is a capacitor with very low inductance, and above a few hundred megahertz it is doing most of the work. Not modelled here.
Where this stops being accurate
- Plane and package parasitics are not modelled — real PDN analysis needs a solver and the package model.
- Ceramic capacitance falls hard with DC bias. A 10 µF X5R at 80% of rated voltage may deliver under half its marked value.
- Capacitance also drifts with temperature and ages. X7R and X5R both lose value over years.
- Below the switching regulator's control bandwidth the regulator, not the capacitors, sets impedance.
- All parts in a bank are assumed identical and identically mounted. Real boards are not that tidy.
Design guidance, not a manufacturing instruction. Verify every result against your fabricator's stack-up and the applicable standard before release. Closed-form models are approximations; the fab's field solver and process window are the authority.
Questions
What people ask about this
What is target impedance and where does the number come from?
Z_target = (Vdd × allowed ripple) / transient current. If a 1.0 V rail may move 5% and the load can step 2 A, the power distribution network has to look like 25 mΩ or less across the whole frequency range where that step has energy. It converts a vague instruction — "add decoupling" — into a number you can actually design against and measure.
What is anti-resonance and why does it matter more than capacitance?
Above its self-resonant frequency a capacitor is inductive. Below it, capacitive. Put a bulk capacitor next to a small one and there is a frequency where the first looks inductive and the second still looks capacitive — they form a parallel LC tank, and the network impedance spikes. That peak can be higher than either capacitor alone, which is why adding a capacitor sometimes makes a rail worse. The plot below shows those peaks explicitly; they are the reason this tool exists.
Why does mounting inductance dominate everything?
Because the capacitor is rarely the problem. The loop from the pad, through the via, to the plane and back is typically 0.5 to 2 nH — often more than the part's own ESL. Above a few tens of megahertz that loop sets the impedance and the capacitance value barely matters. Shorter vias, thinner dielectric to the plane, and pads that do not neck down are worth far more than another decade of capacitors.
Do I really need three different values?
Often not. The instinct to fit 100 µF, 1 µF and 100 nF everywhere comes from application notes, and each additional distinct value adds an anti-resonance peak. Two well-chosen values with enough parts in each bank frequently beats three values with one part each. Drag the counts below and watch what happens to the peaks.
Is a flat impedance curve the goal?
Flat and below target across the band that matters. A deep notch is not a prize — it means one narrow frequency is very well served and the peaks either side are not. What damages a rail is the peak, not the average.
Rail misbehaving under load steps?
PDN problems present as random resets, marginal timing and EMC failures that move when you touch the board. Send us the stack-up and the load profile.