Junction temperature and thermal chain
Die to ambient as a chain of resistances, so you can see which link is actually costing you the temperature.
Junction temperature
—°C
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The physics
Thermal resistance is Ohm's law
T_j = T_ambient + P · θ_ja
θ_ja = θ_jc + θ_cs + θ_sa (series, like resistors)Power is current, temperature difference is voltage, thermal resistance is resistance. Everything you know about series and parallel resistance transfers directly — including the fact that in a series chain the largest element dominates, and improving any of the others changes almost nothing.
That is the practical value of drawing the chain. If θ_sa is 8 °C/W and θ_jc is 0.5 °C/W, a better die-attach is worthless and a bigger heatsink is everything.
Copper pour follows a square root, roughly
θ_pour ≈ k / √(A · t_cu)Spreading resistance falls with area, but not proportionally — heat has to travel laterally through thin copper to reach the far edge, and by the time it gets there the copper is nearly at ambient. Doubling a small pour helps a lot; doubling a large one barely registers. This is why the curve knees, and why chasing pour area past the knee is wasted board space.
Vias couple the layers
A pour on one layer is a two-dimensional heat spreader. A via array turns the stack-up into a three-dimensional one by coupling that pour to every other plane. The improvement is steep for the first several vias and tails off after that — see the via calculator for the shape.
Derating
P_max(T_a) = (T_j,max − T_a) / θ_ja
A part is only rated for its full dissipation at a low ambient. As ambient rises the
allowable power falls linearly to zero at T_j,max. Datasheet derating
curves are exactly this line. Designing at 25 °C ambient and shipping into a sealed
enclosure in a warm climate is how parts that "passed on the bench" fail in the field.
Where this stops being accurate
- The pour model is an approximation of spreading resistance, not a simulation. Real geometry, splits, keep-outs and neighboring parts all matter.
- Steady state only. Short bursts of power are limited by thermal mass, not resistance, and a part can survive far more than this suggests for a few milliseconds.
- Adjacent hot components raise the local ambient — the number to use is the temperature next to the part, not the temperature of the room.
- Airflow factors are broad approximations, and airflow inside an enclosure is rarely what the fan curve suggests.
- Radiation and convection from the board surface are folded into the coefficients rather than modeled.
Design guidance, not a manufacturing instruction. Verify every result against your fabricator's stack-up and the applicable standard before release. Closed-form models are approximations; the fab's field solver and process window are the authority.
Questions
What people ask about this
Why is the datasheet θja almost never the number I get?
Because θja is measured on a specific JEDEC test board — usually 2 or 4 layers with a defined copper area — suspended in still air. Your board is not that board. A part quoted at 40 °C/W on a JEDEC 2s2p can easily be 90 °C/W on a small two-layer board with a token copper pour. Treat θja as a comparison figure between packages, not a prediction. θjc plus your own board and heatsink modeling is the number to design against.
How much copper do I actually need?
The relationship flattens fast. Going from 100 mm² to 400 mm² of pour helps considerably; going from 1000 mm² to 2000 mm² barely registers, because the far copper is nearly at ambient and contributing almost nothing. The curve below shows where your design sits on that knee. Past the knee, spend the effort on thermal vias to the opposite plane instead.
Do thermal vias help enough to bother?
Yes, and they are usually the highest-value change available. A pad with no vias dumps heat into one copper layer; a via array couples it into every plane in the stack-up. The gain is largest on the first eight or so vias and tails off after that — the same diminishing-returns shape as pour area. Our via calculator plots that directly.
What junction temperature should I design to?
Well below the absolute maximum. Silicon lifetime roughly halves for every 10 °C, so a part run continuously at 125 °C when it could be at 95 °C is being thrown away for no reason. A common target is 80% of the rated maximum at the worst-case ambient, which leaves margin for a hot day, a blocked vent, and the part next to it also running hot.
Board runs hot and you are out of ideas?
Thermal problems are usually a layout problem wearing a component costume. We do the stack-up, the pour strategy and the measurement.