Stack-up builder
Assemble the layers, see the finished thickness, get impedance on every signal layer, and check it will not warp.
Finished thickness
—mm
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The build, to scale
Trace widths to hit your targets
| Layer | Type | Reference | Height | Single-ended | Differential |
|---|
Widths are a starting point from closed-form approximations. Send the targets and tolerance to your fabricator and let them return the exact geometry for their press and their prepreg — that is the number that ends up on the board.
What a stack-up decides
Impedance, first
Trace width for a target impedance falls out of the dielectric height and constant. Nothing else on the board depends so completely on a decision made before any routing happens, which is why the stack-up is the first thing to settle on a controlled-impedance design and the most expensive thing to change later.
Symmetry, or the board warps
A multilayer board is pressed under heat and pressure, and the materials shrink differently as they cool. If the construction above the centreline does not mirror the construction below it, the board bows. On a small board with through-hole parts nobody notices; on a large board with fine-pitch BGAs it fails assembly.
Mirror three things: copper weight per layer, dielectric thickness, and core versus prepreg position. The checker below tests all three and tells you where it breaks.
The plane pair is a capacitor
C = ε₀ · εr · A / dTwo planes separated by a thin dielectric form a capacitor with almost no inductance, which makes it the only decoupling that still works above a few hundred megahertz — no discrete capacitor can, because its mounting loop dominates by then. Thinner dielectric between power and ground is nearly free capacitance, and the figure is shown below for a 100 cm² board.
Layer assignment, in order of what matters
- Every signal layer adjacent to a solid plane. No exceptions on anything fast. This sets impedance, controls crosstalk and gives return current somewhere to go.
- Power and ground planes adjacent, on the thinnest dielectric available.
- Never route a fast signal across a plane split. The return current cannot follow, so it takes a long way round, and that loop is an antenna. This causes more EMC failures than any other single layout error.
- Route orthogonally on adjacent signal layers where two must sit next to each other, to keep coupling short.
- Keep the reference plane continuous under a whole net, including under connectors and mounting holes.
Where this stops being accurate
- Impedance comes from closed-form approximations, not a field solver. Expect a few percent, and confirm with your fabricator.
- Pressed prepreg thickness depends on copper distribution — a layer with little copper presses thinner than one that is mostly plane.
- Solder mask lowers outer-layer impedance by roughly 1 to 3 Ω, which is not modelled.
- Copper weight tolerance is typically ±10%, and outer layers gain plating on top of the base foil.
- Glass-weave skew is not modelled and matters above about 10 Gbps.
Design guidance, not a manufacturing instruction. Verify every result against your fabricator's stack-up and the applicable standard before release. Closed-form models are approximations; the fab's field solver and process window are the authority.
Questions
What people ask about this
Why does the stack-up have to be decided before layout?
Because it sets trace width. A 50 Ω line on a 0.075 mm dielectric is about 0.13 mm wide; on 0.2 mm it is about 0.35 mm. If you route first and pick the stack-up later, every controlled-impedance trace is the wrong width and the fix is a re-route, not a parameter change. The stack-up is the first decision on a controlled-impedance board, not the last.
Where should the planes go?
Every signal layer needs a solid reference plane adjacent to it, and the closer the better — spacing to the reference sets impedance, controls crosstalk and gives return current a path. The other rule that matters: put the power and ground planes next to each other with the thinnest dielectric you can, because that pair is a capacitor with almost no inductance and it does the decoupling work above a few hundred megahertz. On four layers this is the classic tension, and the usual answer for mixed-signal work is signal / ground / power / signal.
Why is my stack-up asymmetric and does it matter?
Yes, and it will warp. A board pressed with unequal copper and dielectric above and below its centre bows during reflow — enough to fail assembly on fine-pitch parts. Mirror the construction about the centreline: same copper weights, same prepreg styles, same core positions. Fabricators will usually tell you if you send an asymmetric stack-up, but not always, and not before you have paid for tooling.
What does the fabricator actually need from me?
Layer order with copper weights, dielectric materials and thicknesses, finished board thickness with tolerance, which layers are impedance-controlled with their target and tolerance, and the surface finish. Send the intent rather than an exact construction — fabricators know their own presses and available prepreg, and they will propose a build that hits your impedance targets with materials they stock. A stack-up that specifies a prepreg they do not carry costs you a week.
Stack-up that has to hold impedance in production?
We agree the build with the fabricator before layout starts, and we specify it the way they want to receive it. Send us the interface list and the board outline.