Via current capacity and thermal via calculator
What one barrel carries, how many you need for a current, and how much a thermal via array actually buys you.
Vias needed for this current
—vias
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The physics
A plated via is a copper tube, not a rod. Its conducting cross-section is the annulus of plating around the hole, and that is a much smaller number than the hole diameter suggests — which is the whole reason vias surprise people.
Cross-section
A = π · (d/2 + p)² − π · (d/2)² hollow, plating p
A = π · (d/2 + p)² copper filledA 0.3 mm hole with 25 µm plating gives about 0.026 mm² — comparable to a 0.75 mm trace in 1 oz copper, and rather less than the power trace that is probably feeding it.
Current capacity
I = k · ΔT^0.44 · A^0.725 k = 0.024, treated as internalThe same IPC-2221B relation used for traces, with the internal constant — a via is surrounded by laminate on all sides and cannot convect. Divide the net current by the per-via figure and round up; that is the via count the path needs.
Thermal resistance
θ = L / (k_cu · A) k_cu = 385 W/m·K
N vias in parallel: θ_array = θ / NVias in parallel divide thermal resistance, so the first few help enormously and the last few barely register. Doubling four to eight is worth doing; doubling thirty-two to sixty-four is usually not, because by then the via array has stopped being the dominant term in the junction-to-ambient chain and something else — the spreading plane, the enclosure — has taken over.
Where this stops being accurate
- Laminate conduction is ignored. Real heat also travels through the FR-4 around the barrel, so this is conservative for thermal work.
- The plane on the far side matters more than the vias. An array dumping into a small isolated pour achieves very little.
- Solder wicking into unfilled via-in-pad changes both the thermal and the assembly picture, and is why tented or filled vias exist.
- Plating thickness varies across a panel and down a barrel. The minimum is what carries the current.
- Aspect ratio limits plating. A thick board with a small hole plates less reliably; most fabs cap at around 8:1 to 10:1.
Design guidance, not a manufacturing instruction. Verify every result against your fabricator's stack-up and the applicable standard before release. Closed-form models are approximations; the fab's field solver and process window are the authority.
Questions
What people ask about this
How much current can one via actually carry?
Far less than people assume. A 0.3 mm barrel with 25 µm plating has roughly the cross-section of a 0.2 mm trace — under an amp for a 10 °C rise. The instinct that "a via is basically a wire" is wrong; the barrel is a thin copper tube, not a solid conductor, and the plating thickness is what carries the current.
Why is via count so often the real constraint?
Because a designer sizes a 3 mm power trace correctly and then necks it through two vias to change layer. Those two vias are now the limiting element of the entire path, and they are the thing that runs hot. Whenever a current-carrying net changes layer, count the vias against the current — it takes ten seconds and it catches a genuine class of failure.
How many thermal vias do I need under a package?
Enough that the array thermal resistance stops dominating the junction-to-ambient chain. Vias in parallel divide resistance, so the return diminishes fast — going from four to eight vias helps a lot, sixteen to thirty-two helps far less. The tool shows where the curve flattens, which is usually the sensible stopping point.
Does filling or capping vias change anything?
Thermally, yes — a copper-filled via is a solid conductor rather than a tube and conducts substantially better. Conductive-fill and via-in-pad both cost money and both need to be agreed with the fabricator early because they change the process. Electrically, the improvement is real but smaller than the thermal one.
Power path changing layers?
Via count is the most commonly missed constraint on an otherwise well-sized power net. Send us the stack-up and the current and we'll check the whole path, not just the trace.